Conventional first-in first-out memory interfaces (FIFO interfaces) are often used to temporarily store data that is being shared between two or more external devices. As the name implies, data that is received from an external input device is stored in sequential order and subsequently provided to the external output device in the same sequential order. FIFO interfaces are typically employed to accommodate external devices that operate asynchronously, because the FIFO interface can receive the input data at an input rate that is different from the output rate. Thus, the FIFO interface allows the external devices to share data although each device is communicating at different rates. Such a FIFO interface is considered a rate matching FIFO. FIFO interfaces are extremely useful in systems that have a plurality of external devices that share a common resource, such as, for example, a high-speed or low-speed communication link or bus. By way of example, FIFO interfaces are often used in computer systems having a plurality of input/output (I/O) devices and in communication systems having a plurality of devices coupled to a communication medium. In these systems, a FIFO interface stores the data received until such time that the receiving device can process the data.
FIG. 1 is a block diagram depicting a system 10 having at least one input device 12 that is configured to share data through a FIFO interface 14 to at least one output device 16. Input device 12 and output device 16 represent circuits or devices, each of which is typically separate from one another and FIFO interface 14. As shown, input device 12 is typically configured to send and/or receive one or more control signals to and/or from FIFO interface 14 to coordinate the transfer of data from input device 12 to FIFO interface 14. For example, to send data to FIFO 14, input device 12 asserts a write request signal that causes FIFO interface 14 to "shift in" or store the data provided by input device 12. FIFO 14 will accept and store the data in this manner until such time as FIFO interface 14 reaches a predetermined or full state in which case FIFO 14 will no longer accept additional input data from input device 12. Once FIFO interface 14 has stored data from input device 12, output device 16 can assert a read request signal that causes FIFO interface 14 to "shift out" or retrieve the stored data. The stored data will be provided to output device 16 in the same sequence as stored by input device 12.
FIFO interface 14 typically includes a dual-ported random access memory (RAM) having a specific configuration. A conventional dual-ported RAM has a data port dedicated for use by input device 12 and a separate data port dedicated for use by output device 16 and is configured to allow input device 12 and output device 16 to simultaneously access different stored data.
The configuration of FIFO interface 14, and in particular the configuration of the dual-ported RAM (e.g., the addressing scheme, data width, memory length and speed), define the types of applications and systems in which FIFO interface 14 can properly function. Therefore, manufacturers of FIFO interfaces typically provide a variety of different configurations that can be used in many applications and systems. For applications having unique FIFO interface requirements, several design techniques have been developed in order to meet the system's requirements, such as, for example, cascading several FIFO interfaces and/or adding additional circuitry. Unfortunately, configuring a unique FIFO interface from available FIFO interfaces and circuitry can greatly increase the cost, waste space and/or power, and limit the system's effectiveness. Thus, there is a need for a configurable FIFO interface that can support the unique requirements of such systems.